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1 tm file number 3191.2 hs-82c55arh radiation hardened cmos programmable peripheral interface the intersil hs-82c55arh is a high performance, radiation hardened cmos version of the industry standard 8255a and is manufactured using a hardened ?ld, self-aligned silicon gate cmos process. it is a general purpose programmable i/o device which may be used with many different microprocessors. there are 24 i/o pins which are organized into two 8-bit and two 4-bit ports. each port may be programmed to function as either an input or an output. additionally, one of the 8-bit ports may be programmed for bidirectional operation, and the two 4-bit ports can be programmed to provide handshaking capabilities. the high performance, radiation hardness, and industry standard con?uration of the hs-82c55arh make it compatible with the hs-80c86rh radiation hardened microprocessor. static cmos circuit design insures low operating power. bus hold circuitry eliminates the need for pull-up resistors. the intersil hardened ?ld cmos process results in performance equal to or greater than existing radiation resistant products at a fraction of the power. speci?ations for rad hard qml devices are controlled by the defense supply center in columbus (dscc). the smd numbers listed here must be used when ordering. detailed electrical speci?ations for these devices are contained in smd 5962-95819. a ?ot-link?is provided on our homepage for downloading. www.intersil.com/spacedefense/space.asp features electrically screened to smd # 5962-95819 qml quali?d per mil-prf-38535 requirements radiation hardened - total dose. . . . . . . . . . . . . . . . . . . . . 100 krad(si) (max) - transient upset . . . . . . . . . . . . . . . . . . . . <10 8 rad(si)/s - latch up free epi-cmos low power consumption - iddsb. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 a pin compatible with nmos 8255a and the intersil 82c55a high speed, no ?ait state?operation with 5mhz hs-80c86rh 24 programmable i/o pins bus-hold circuitry on all i/o ports eliminates pull-up resistors direct bit set/reset capability enhanced control word read capability hardened field, self-aligned, junction isolated cmos process single 5v supply 2.0ma drive capability on all i/o port outputs military temperature range . . . . . . . . . . . -55 o c to 125 o c pinout ceramic dual-in-line metal seal package (sbdip) mil-std-1835 cdip2-t40 top view ordering information ordering number internal mkt. number temp. range ( o c) 5962r9581901qqc HS1-82C55ARH-8 -55 to 125 5962r9581901vqc hs1-82c55arh-q -55 to 125 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 pa3 pa2 pa1 pa0 rd cs gnd a1 a0 pc7 pc6 pc5 pc4 pc0 pc1 pc2 pc3 pb0 pb1 pb2 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 pa4 pa5 pa6 pa7 wr reset d0 d1 d2 d3 d4 d5 d6 d7 vdd pb7 pb6 pb5 pb4 pb3 data sheet august 2000 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil and design is a trademark of intersil corporation. | copyright ?intersil corporation 2000
2 pin descriptions symbol pin numbers type description pa0-7 1-4, 37-40 i/o port a: general purpose i/o port. data direction and mode is determined by the contents of the control word. pb0-7 18-25 i/o port b: general purpose i/o port. see port a. pc0-3 14-17 i/o port c (lower): combination i/o port and control port associated with port b. see port a. pc4-7 10-13 i/o port c (upper): combination i/o port and control port associated with port a. see port a. d0-7 27-34 i/o bidirectional data bus: three-state data bus enabled as an input when cs and wr are low and as an output when cs and rd are low. vdd 26 i vdd: the +5v power supply pin. a 0.1 f capacitor between pins 26 and 7 is recommended for decoupling. gnd 7 i ground . cs 6 i chip select: a ?ow?on this input pin enables the communication between the hs-82c55arh and the cpu. rd 5 i read: a ?ow on this input pin enables the hs-82c55arh to send the data or status information to the cpu on the data bus. in essence, it allows the cpu to ?ead from?the hs-82c55arh. wr 36 i write : a ?ow?on this input pin enables the cpu to write data or control words into the hs-82c55arh. a0 and a1 8, 9 i port select 0 and port select 1: these input signals, in conjunction with the rd and wr inputs, control the selection of one of the three ports or the control word registers. they are normally connected to the least significant bits of the address bus (a0 and a1). reset 35 i reset: a ?igh on this input clears the control register and all ports (a, b, c) are set to the input mode. ?us hold devices internal to the hs-82c55arh will hold the i/o port inputs to a logic ? state with a maximum hold current of 400 a. hs-82c55arh
3 functional diagram ac test circuit note: includes stray and jig capacitance. ac testing input, output waveforms note: ac testing: all parameters tested as per test circuits. input rise and fall times are driven at 1v/ns. group a control power supplies data bus buffer group b control read/write control logic rd wr a1 a0 reset cs d7 - d0 bidirectional data bus +5v gnd 8-bit internal data bus group b port b (8) group b port c lower (4) group a port c upper (4) group a port a (8) i/o pa7 - pa0 i/o pc7 - pc4 i/o pc3 - pc0 i/o pb7 - pb0 test conditions definition table v1 r1 r2 c1 1.7v 523 ? open 150pf test point from output under test v1 r1 r2 c1 (note) 1.5v 1.5v 0.4v input 2.8v hs-82c55arh
4 waveforms figure 1. mode 0 (basic input) figure 2. mode 0 (basic output) figure 3. mode 1 (strobed input) figure 4. mode 1 (strobed output) figure 5. mode 2 (bidirectional) note: any sequence where wr occurs before a ck and stb occurs before rd is permissible. figure 6. write timing figure 7. read timing rd input cs, a1, a0 d7 - d0 tpvrl trhpx trlrh tavrl trhax trldv trhdz wr d7 - d0 cs, a1, a0 output twlwh tdvwh twhdx tavwl twhpv twhax stb ibf intr rd input from peripheral tslsh tslih tshpx tpvsh trhil trlnl tshnh wr obf intr a ck output twlnl twhol tkloh twhpv tklkh tkhnh wr obf intr a ck stb ibf peripheral bus rd data from cpu to hs-82c55arh twhol tslih tkloh tklkh data from peri- pheral to data from hs-82c55arh hs-82c55arh to peripheral data from hs-82c55arh to cpu tslsh tklpv tkhpx tpvsh tshpx trhil a0 - a1, cs data bus wr tavwl twhax twlwh twhdx tdvwh a0 - a1, cs rd data bus tavrl trhax high impedance valid high impedance trlrh tavrl trhdx hs-82c55arh
5 burn-in circuits programmable peripheral interface static configuration notes: 1. vdd = 6.0v 0.5% 2. idd <500 a 3. t a min = 125 o c programmable peripheral interface dynamic configuration notes: 4. vdd = 6.0v 5% for burn-in 5. vdd = 5.0v 5% for life test 6. all resistors are 10k ? 5% 7. -0.3v vil 0.8v 8. vdd - 1.0v vih vdd 9. idd < 5ma 10. f0 = 10khz, 50% duty cycle 11. f1 = f0/2; f2 = f1/2; f3 = f2/2; f4 = f3/2 . . . f7 = f6/2 12. t a min = 125 o c 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 vdd 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 f0 f4 f6 f5 f7 f3 vdd f0 f2 f1 f5 f0 f0 f4 hs-82c55arh
6 functional description the hs-82c55arh is a programmable peripheral interface designed to allow microcomputer systems to control and interface with all types of peripheral devices. it has the ability to generate and respond to all asynchronous handshaking signals necessary to transfer data to and from peripheral devices, and it can also interrupt the processor when a peripheral needs servicing. these capabilities allow the hs-82c55arh to be used in an unlimited number of applications including external system control, asynchronous data transfer, and systems monitoring. data bus buffer this three-state bidirectional 8-bit buffer is used to interface the hs-82c55arh to the system data bus (see figure 8). data is transmitted or received by the buffer upon execution of input or output instructions by the cpu. control words and status information are also transferred through the data bus buffer. read/write and control logic the function of this block is to manage all of the internal and external transfer of both data and control or status words. it accepts inputs from the cpu address and control busses and in turn, issues commands to both of the control groups. group a and group b controls the functional con?uration of each port is programmed by the systems software. in essence, the cpu writes a control word to the hs-82c55arh. the control word contains information such as ?ode? ?it set? ?it reset? etc., that initializes the functional con?uration of the hs-82c55arh. each of the control blocks (group a and group b) accepts ?ommands?from the read/write control logic, receives ?ontrol words?from the internal data bus and issues the proper commands to its associated ports. control group - port a and port c upper (c7 - c4). control group - port b and port c lower (c3 - c0). ports a, b, c the hs-82c55arh contains three 8-bit ports (a, b and c). all can be con?ured to a wide variety of functional characteristics by the system software but each has its own special features or ?ersonality?to further enhance the power and ?xibility of the hs-82c55arh. irradiation circuit cmos programmable peripheral interface note: 13. vdd = 5.5v 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 +5.5v +5.5v port a one 8-bit data output latch/buffer and one 8-bit data input latch. both ?ull-up and ?ull-down bus hold devices are present on port a. see figure 9a. port b one 8-bit data input/output latch/buffer and one 8-bit data input buffer. see figure 9b. group power supplies data bus buffer group read/ rd wr a1 a0 reset cs d7- bidirectional data bus +5v gnd 8-bit internal data bus group b port b (8) group b port c lower group a port c upper group a port a (8) i/o pa7- write control logic d0 pa0 i/o pc7- pc4 i/o pc3- pc0 i/o pb7- pb0 a control b control (4) (4) figure 8. block diagram data bus buffer, read/write, group a and b control logic functions hs-82c55arh
7 operational description control word the data direction and mode of ports a, b and c are determined by the contents of the control word. see figure 11. the control word can be both written and read as shown in table 1 and 2. during write operations, the function of the control word being written is determined by data bit d7. if d7 is low, the data on d0 - d3 will set or reset one of the bits of port c. see figure 12. during read operations, the control word will always be in the format illustrated in figure 11 with bit d7 high to indicate control word mode information. port c one 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input). this port can be divided into two 4-bit ports under the mode control. each 4-bit port contains a 4-bit latch and can be used for the control signal outputs and status signal inputs in conjunction with ports a and b. see figure 9b. figure 9a. figure 9b. figure 9. i/o port configuration master reset internal data in internal data out wr signal rd control external port a pin master reset internal data in internal data out wr signal external port b, c p vdd pin table 1. a1 a0 rd wr cs input operation (read) 00010 port a - data bus 01010 port b - data bus 10010 port c - data bus 11010 control word - data bus table 2. a1 a0 rd wr cs output operation (write) 00100 data bus - port a 01100 data bus - port b 10100 data bus - port c 11100 data bus - control word table 3. a1 a0 rd wr cs disable function xxxx1 data bus - 3-state rd, wr d7 - d0 a0 - a1 bca cs 8 4 8 4 i/o i/o i/o i/o pb7 - pb0 pc3 - pc0 pc7 - pc4 pa7 - pa0 mode 0 data bus control bus address bus bca 8 8 i/o i/o pb7 - pb0 pa7 - pa0 mode 1 control or i/o control or i/o bca 8 8 i/o bidirec- pb7 - pb0 pa7 - pa0 mode 2 i/o control tional figure 10. basic mode definitions and bus interface hs-82c55arh
8 mode selection there are three basic modes of operation that can be selected by the system software: mode 0 - basic input/output mode 1 - strobed input/output mode 2 - bidirectional bus when the reset input goes ?igh? all ports will be set to the input mode with all 24 port lines held at the logic ?ne level by internal bus hold devices. after reset, the hs-82c55arh can remain in the input mode with no additional initialization required. this eliminates the need for pull-up or pull-down resistors in all cmos designs. during the execution of the system program, any of the other modes may be selected using a single output instruction. this allows a single hs-82c55arh to service a variety of peripheral devices with a simple software maintenance routine. the modes for port a and port b can be separately de?ed while port c is divided into two portions as required by the port a and port b de?itions. all of the output registers, including the status register, will be reset whenever the mode is changed. modes may be combined so that their functional de?ition can be ?ailored?to almost any i/o structure. for instance: group b can be programmed in mode 0 to monitor simple switch closings or display computational results, group a could be programmed in mode 1 to monitor a keyboard or tape recorder on an interrupt-driven basis. the mode de?itions and possible mode combinations may seem confusing at ?st but after a cursory review of the complete device operation a simple, logical i/o approach will surface. the design of the hs-82c55arh has taken into account things such as ef?ient pc board layout, control signal de?ition vs pc layout and complete functional ?xibility to support almost any peripheral device with no external logic. such design represents the maximum use of the available pins. single bit/set/reset feature any of the eight bits of port c can be set or reset using a single output instruction. see figure 12. this feature reduces software requirements in control-based applications. interrupt control functions when the hs-82c55arh is programmed to operate in mode 1 or mode 2, control signals are provided that can be used as interrupt request inputs to the cpu. the interrupt request signals, generated from port c, can be inhibited or enable by setting or resetting the associated inte ?p-?p, using the bit set/reset function of port c. this function allows the programmer to enable or disable a cpu interrupt by a speci? i/o device without affecting any other device in the interrupt structure. inte flip-flop de?ition: (bit-set) - inte is set - interrupt enable. (bit-reset) - inte is reset - interrupt disable. note: all mask ?p-?ps are automatically reset during mode selection and device reset. x x 1 1 0 data bus - 3-state table 3. a1 a0 rd wr cs disable function d7 d6 d5 d4 d3 d2 d1 d0 control word group b port c (lower) 1 = input 0 = output port b 1 = input 0 = output mode selection 0 = mode 0 1 = mode 1 group a port c (upper) 1 = input 0 = output port a 1 = input 0 = output mode selection 00 = mode 0 01 = mode 1 1x = mode 2 mode set flag 1 = active figure 11. mode set control word format d7 d6 d5 d4 d3 d2 d1 d0 control word bit set/reset 1 = set 0 = reset bit select 0 0 0 0 1 1 0 0 2 0 1 0 3 1 1 0 4 0 0 1 5 1 0 1 6 0 1 1 7 1 1 1 b0 b1 b2 bit set/reset flag 0 = active don? care xxx figure 12. bit set/reset control word format hs-82c55arh
9 operating modes mode 0 (basic input/output) this functional con?uration provides simple input and output operations for each of the three ports. no handshaking it required, data is simply written to or read from a speci? port. mode 0 basic functional de?itions: two 8-bit ports and two 4-bit ports any port can be input or output outputs are latched inputs are not latched 16 different input/output con?urations possible figure 13. mode 0 (basic input) figure 14. mode 0 (basic output) trlrh tpvrl trhpx tavrl trhax trldv trhdx rd input cs, a1, a0 d7 - d0 wr d7 - d0 cs, a1, a0 output twlwh tdvwh twhdx tavwl twhax twhpv hs-82c55arh
10 mode 0 port de?ition a b group a no. group b d4 d3 d1 d0 port a port c (upper) port b port c (lower) 0 0 0 0 output output 0 output output 0 0 0 1 output output 1 output input 0 0 1 0 output output 2 input output 0 0 1 1 output output 3 input input 0 1 0 0 output input 4 output output 0 1 0 1 output input 5 output input 0 1 1 0 output input 6 input output 0 1 1 1 output input 7 input input 1 0 0 0 input output 8 output output 1 0 0 1 input output 9 output input 1 0 1 0 input output 10 input output 1 0 1 1 input output 11 input input 1 1 0 0 input input 12 output output 1 1 0 1 input input 13 output input 1 1 1 0 input input 14 input output 1 1 1 1 input input 15 input input mode 0 con?urations control word #0 control word #1 control word #2 control word #3 d7 d6 d5 d4 d3 d2 d1 d0 10000000 a c b 8 4 4 8 pa7 - pa0 pc7 - pc4 pc3 - pc0 pb7 - pb0 d7 - d0 d7 d6 d5 d4 d3 d2 d1 d0 10000001 a c b 8 4 4 8 pa7 - pa0 pc7 - pc4 pc3 - pc0 pb7 - pb0 d7 - d0 d7 d6 d5 d4 d3 d2 d1 d0 10000010 a c b 8 4 4 8 pa7 - pa0 pc7 - pc4 pc3 - pc0 pb7 - pb0 d7 - d0 d7 d6 d5 d4 d3 d2 d1 d0 10000011 a c b 8 4 4 8 pa7 - pa0 pc7 - pc4 pc3 - pc0 pb7 - pb0 d7 - d0 hs-82c55arh
11 control word #4 control word #5 control word #6 control word #7 control word #8 control word #9 control word #10 control word #11 mode 0 con?urations (continued) d7 d6 d5 d4 d3 d2 d1 d0 10001000 a c b 8 4 4 8 pa7 - pa0 pc7 - pc4 pc3 - pc0 pb7 - pb0 d7 - d0 d7 d6 d5 d4 d3 d2 d1 d0 10011001 a c b 8 4 4 8 pa7 - pa0 pc7 - pc4 pc3 - pc0 pb7 - pb0 d7 - d0 d7 d6 d5 d4 d3 d2 d1 d0 10001010 a c b 8 4 4 8 pa7 - pa0 pc7 - pc4 pc3 - pc0 pb7 - pb0 d7 - d0 d7 d6 d5 d4 d3 d2 d1 d0 10001011 a c b 8 4 4 8 pa7 - pa0 pc7 - pc4 pc3 - pc0 pb7 - pb0 d7 - d0 d7 d6 d5 d4 d3 d2 d1 d0 10010000 a c b 8 4 4 8 pa7 - pa0 pc7 - pc4 pc3 - pc0 pb7 - pb0 d7 - d0 d7 d6 d5 d4 d3 d2 d1 d0 10010001 a c b 8 4 4 8 pa7 - pa0 pc7 - pc4 pc3 - pc0 pb7 - pb0 d7 - d0 d7 d6 d5 d4 d3 d2 d1 d0 10010010 a c b 8 4 4 8 pa7 - pa0 pc7 - pc4 pc3 - pc0 pb7 - pb0 d7 - d0 d7 d6 d5 d4 d3 d2 d1 d0 10010011 a c b 8 4 4 8 pa7 - pa0 pc7 - pc4 pc3 - pc0 pb7 - pb0 d7 - d0 hs-82c55arh
12 operating modes mode 1 (strobed input/output) this functional con?uration provides a means for transferring i/o data to or from a speci?d port in conjunction with strobes or ?andshaking signals. in mode 1, port a and port b use the lines on port c to generate or accept these ?andshaking?signals. mode 1 basic functional de?itions: two groups (group a and group b) each group contains one 8-bit port and one 4-bit control/data port. the 8-bit data port can be either input or output. both inputs and outputs are latched. the 4-bit port is used for control and status of the 8-bit port. input control signal de?ition stb (strobe input) a ?ow?on this input loads data into the input latch. ibf (input buffer full f/f) a ?igh?on this output indicates that the data has been loaded into the input latch; in essence, an acknowledgment. ibf is set by stb input being low and is reset by the rising edge of the rd input. intr (interrupt request) a ?igh?on this output can be used to interrupt the cpu when an input device is requesting service. intr is set by the rising edge of stb and reset by the falling edge of rd. this procedure allows an input device to request service from the cpu by simply strobing its data into the port. inte a controlled by bit set/reset of pc4. inte b controlled by bit set/reset of pc2. control word #12 control word #13 control word #14 control word #15 mode 0 con?urations (continued) d7 d6 d5 d4 d3 d2 d1 d0 10011000 a c b 8 4 4 8 pa7 - pa0 pc7 - pc4 pc3 - pc0 pb7 - pb0 d7 - d0 d7 d6 d5 d4 d3 d2 d1 d0 10011001 a c b 8 4 4 8 pa7 - pa0 pc7 - pc4 pc3 - pc0 pb7 - pb0 d7 - d0 d7 d6 d5 d4 d3 d2 d1 d0 10011010 a c b 8 4 4 8 pa7 - pa0 pc7 - pc4 pc3 - pc0 pb7 - pb0 d7 - d0 d7 d6 d5 d4 d3 d2 d1 d0 10011011 a c b 8 4 4 8 pa7 - pa0 pc7 - pc4 pc3 - pc0 pb7 - pb0 d7 - d0 inte a pc6, 7 1 = input 0 = output d7 d6 d5 d4 d3 d2 d1 d0 1 control word mode 1 (port b) 11 pa7 - pa0 pc4 pc5 pc3 pc6, 7 rd 8 stb ibf intr i/o 2 inte b pb7 - pb0 pc2 pc1 pc0 rd 8 stb ibf intr b b b a a a d7 d6 d5 d4 d3 d2 d1 d0 10111/0 control word mode 1 (port a) figure 15. mode 1 input hs-82c55arh
13 output control signal de?ition obf (output buffer full f/f) the obf output will go ?ow?to indicate that the cpu has written data out to the speci?d port. this does not mean valid data is sent out of the port at this time since obf can go true before data is available. data is guaranteed valid at the rising edge of obf. see note 1. the obf f/f will be set by the rising edge of the wr input and reset by ack input being low. ack (acknowledge input) a ?ow on this input informs the hs-82c55arh that the data from port a or port b is ready to be accepted. in essence, a response from the peripheral device indicating that it is ready to accept data. see note 14. intr (interrupt request) a ?igh?on this output can be used to interrupt the cpu when an output device has accepted data transmitted by the cpu. intr is set by the rising edge of ack and reset by the falling edge of wr. inte a controlled by bit set/reset of pc6. inte b controlled by bit set/reset of pc2. note: 14. to strobe data into the peripheral device, the user must operate the strobe line in a hand shaking mode. the user needs to send obf to the peripheral device, generate an a ck from the peripheral device and then latch data into the peripheral device on the rising edge of obf. combinations of mode 1: port a and port b can be individually de?ed as input or output in mode 1 to support a wide variety of strobed i/o applications. stb ibf intr rd input from peripheral tslsh tslih tshpx tpvsh trhil trlnl tshnh figure 16. mode 1 (strobed input) inte a d7 d6 d5 d4 d3 d2 d1 d0 1 control word mode 1 (port b) 10 pa7 - pa0 pc7 pc6 pc3 pc4, 5 wr 8 obf a ck intr i/o 2 a a a inte b pb7 - pb0 pc1 pc2 pc0 wr 8 obf a ck intr b b b d7 d6 d5 d4 d3 d2 d1 d0 10101/0 control word pc4, 5 1 = input 0 = output mode 1 (port a) figure 17. mode 1 output wr obf intr a ck output twlnl twhol tkhol twhpv tklkh tkhnh figure 18. mode 1 (strobed output) d7 d6 d5 d4 d3 d2 d1 d0 1 control word port a (strobed input) 10 port b (strobed output) 0 1 1 1/0 pc6, 7 1 = input 0 = output pa7 - pa0 pc4 pc5 pc6, 7 wr 8 stb a ibf a intr a pc3 pb7 - pb0 pc1 pc2 pc0 i/o obf b a ck b intr b 8 2 rd d7 d6 d5 d4 d3 d2 d1 d0 1 control word port a (strobed output) 11 port b (strobed input) 0 1 0 1/0 pc4, 5 1 = input 0 = output pa7 - pa0 pc7 pc6 pc4, 5 rd 8 obf a a ck a intr a pc3 pb7 - pb0 pc2 pc1 pc0 i/o stb b ibf b intr b 8 2 wr figure 19. combinations of mode 1 hs-82c55arh
14 operating modes mode 2 (strobed bidirectional bus i/o) the functional con?uration provides a means for communicating with a peripheral device or structure on a single 8-bit bus for both transmitting and receiving data (bidirectional bus i/o). ?andshaking?signals are provided to maintain proper bus ?w discipline similar to mode 1. interrupt generation and enable/disable functions are also available. mode 2 basic functional de?itions: used in group a only. one 8-bit, bidirectional bus port (port a) and a 5-bit control port (port c). both inputs and outputs are latched. the 5-bit control port (port c) is used for control and status for the 8-bit, bidirectional bus port (port a). bidirectional bus i/o control signal de?ition intr (interrupt request) a high on this output can be used to interrupt the cpu for both input or output operations. intr will be set either by the rising edge of a ck (inte1 = 1) or the rising edge of stb (inte2 = 1). intr will be reset by the falling edge of wr (if previously set by the rising edge or a ck), the falling edge of rd (if previously set by the rising edge of stb), or the falling edge of wr when immediately following a low rd pulse or the falling edge of rd when immediately following a low wr pulse (if previously set by the rising edges of both a ck and stb). output operations obf (output buffer full) the obf output will go ?ow?to indicate that the cpu has written data out to port a. a ck (acknowledge) a ?ow?on this input enables the three-state output buffer of port a to send out the data. otherwise, the output buffer will be in the high impedance state. inte 1 (the inte flip-flop associated with obf) controlled by bit set/reset of pc6. input operations stb (strobe input) a ?ow?on this input loads data into the input latch. ibf (input buffer full f/f) a ?igh?on this output indicates that data has been loaded into the input latch. inte 2 (the inte flip-flop associated with ibf) controlled by bit set/reset of pc4. d7 d6 d5 d4 d3 d2 d1 d0 1 control word 0 1/0 1/0 1/0 pc2 - pc0 1 = input 0 = output port b 1 = input 0 = output group b mode 0 = mode 0 1 = mode 1 figure 20. mode control word inte 2 pc7 pc6 pc3 pc2- pc0 wr 8 stb a ibf a intr a i/o 3 rd pc7 pc6 obf a a ck a inte 1 pa7- pa0 figure 21. mode 2 (bidirectional) wr obf intr a ck stb ibf peripheral bus rd data from cpu to hs-82c55arh twhol tslih tkhol tklkh data from peri- pheral to data from hs-82c55arh hs-82c55arh to peripheral data from hs-82c55arh to cpu tslsh tklpv tkhpx tpvsh tshpx trhil note: any sequence where wr occurs before a ck and stb occurs before rd is permissible. figure 22. mode 2 (bidirectional) hs-82c55arh
15 special mode combination considerations there are several combinations of modes possible. for any combination, some or all of port c lines are used for control or status. the remaining bits are either inputs or outputs as de?ed by a ?et mode?command. during a read of port c, the state of all the port c lines, except the a ck and stb lines, will be placed on the data bus. in place of the ack and stb line states, ?g status will appear on the data bus in the pc2, pc4, and pc6 bit positions as illustrated by figure 25. through a ?rite port c?command, only the port c pins programmed as outputs in a mode 0 group can be written. no other pins can be affected by a ?rite port c command, nor can the interrupt enable ?gs be accessed. to write to any port c output programmed as an output in a mode 1 group or to change an interrupt enable ?g, the ?et/reset port c bit?command must be used. with a ?et/reset port c bit?command, any port c line programmed as an output (including ibf and obf) can be written, or an interrupt enable ?g can be either set or reset. port c lines programmed as inputs, including a ck and stb lines, associated with port c fare not affected by a ?et/ reset port c bit?command. writing to the corresponding port c bit positions of the a ck and stb lines with the ?et/ reset port c bit?command will affect the group a and group b interrupt enable ?gs, as illustrated in figure 25. mode definition summary mode 0 mode 1 mode 2 in out in out group a only pa0 ap1 pa2 pa3 pa4 pa5 pa6 pa7 in in in in in in in in out out out out out out out out in in in in in in in in out out out out out out out out pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 in in in in in in in in out out out out out out out out in in in in in in in in out out out out out out out out - - - - - - - - pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 in in in in in in in in out out out out out out out out intr b ibf b stb b intr a stb a ibf a i/o i/o intr b obf b a ck b intr a i/o i/o a ck a obf a i/o i/o i/o intr a stb a ibf a a ck a obf a mode 0 or mode 1 only input configuration d7 d6 d5 d4 d3 d2 d1 d0 i/o i/o ibfa intea intra inteb ibfb intrb group a group b output configuration d7 d6 d5 d4 d3 d2 d1 d0 obfa intea i/o i/o intra inteb obfb intrb group a group b figure 23. mode 1 status word format d7 d6 d5 d4 d3 d2 d1 d0 obfa inte1 ibfa inte2 intra x x x group a group b note: (de?ed by mode 0 or mode 1 selection) figure 24. mode 2 status word format hs-82c55arh
16 current drive capability any output on port a, b or c can sink or source 2.5ma. this feature allows the 82c55a to directly drive darlington type drivers and high-voltage displays that require such sink or source current. reading port c status (figures 23 and 24) in mode 0, port c transfers data to or from the peripheral device. when the 82c55a is programmed to function in modes 1 or 2, port c generates or accepts ?and shaking signals with the peripheral device. reading the contents of port c allows the programmer to test or verify the ?tatus of each peripheral device and change the program ?w accordingly. there is no special instruction to read the status information from port c. a normal read operation of port c is executed to perform this function. interrupt enable flag position alternate port c pin signal (mode) inte b pc2 a ckb (output mode 1) or stbb (input mode 1) inte a2 pc4 stba (input mode 1 or mode 2) inte a1 pc6 a cka (output mode 1 or mode 2) figure 25. interrupt enable flags in modes 1 and 2 hs-82c55arh
17 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?ation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site www.intersil.com sales of?e headquarters north america intersil corporation p. o. box 883, mail stop 53-204 melbourne, fl 32902 tel: (321) 724-7000 fax: (321) 724-7240 europe intersil sa mercure center 100, rue de la fusee 1130 brussels, belgium tel: (32) 2.724.2111 fax: (32) 2.724.22.05 asia intersil ltd. 8f-2, 96, sec. 1, chien-kuo north, taipei, taiwan 104 republic of china tel: 886-2-2515-8508 fax: 886-2-2515-8369 die characteristics die dimensions: 3420 m x 4350 m x 485 m 25 m interface materials: glassivation: type: sio2 thickness: 8k ? 1k ? top metallization: type: al/si thickness: 11k ? 2k ? additional information: worst case current density: 7.7 x 10 4 a/cm 2 metallization mask layout hs-82c55arh (5) rd (4) pa0 (3) pa1 (2) pa2 (1) pa3 (40) pa4 (39) pa5 (38) pa6 (37) pa7 (36) wr reset (35) d0 (34) d1 (33) d2 (32) d3 (31) d4 (30) d5 (29) d6 (28) d7 (27) vdd (26) (6) cs (7) vss (8) a1 (9) a0 (10) pc7 (11) pc6 (12) pc5 (13) pc4 (14) pc0 (15) pc1 pc2 (16) pc3 (17) pb0 (18) pb1 (19) pb2 (20) pb3 (21) pb4 (22) pb5 (23) pb6 (24) pb7 (25) hs-82c55arh

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